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em44dm1688lbb nov. 2011 1/29 www.eorex.com revision history revision 0.1 (nov. 2011) -first release.
em44dm1688lbb nov. 2011 2/29 www.eorex.com 2gb (16m8 bank 16) double data rate 2 sdram features ? jedec standard vdd/vddq = 1.8v 0.1v. ? all inputs and outputs are compatible with sstl_18 interface. ? fully differential clock inputs (ck, /ck) operation. ? eight banks ? posted cas ? bust length: 4 and 8. ? programmable cas latency (cl): 5, 7 ? programmable additive latency (al): 0, 1, 2, 3, 4, 5 & 6. ? write latency (wl) =read latency (rl) -1. ? read latency (rl) = programmable additive latency (al) + cas latency (cl) ? bi-directional differential data strobe (dqs). ? data inputs on dqs centers when write. ? data outputs on dqs, /dqs edges when read. ? on chip dll align dq, dqs and /dqs transition with ck transition. ? dm mask write data-in at the both rising and falling edges of the data strobe. ? sequential & interleaved burst type available. ? off-chip driver (ocd) impedance adjustment ? on die termination (odt) ? auto refresh and self refresh ? 8,192 refresh cycles / 64ms ? average refresh period 7.8us ? rohs compliance ? high temperature self-refresh rate enable description the em44dm1688lbb is a high speed double date rate 2 (ddr2) synchronous dram fabricated with ultra high performance cmos process containing 2,147,483,648 bits which organized as 16mbits x 8 banks by 16 bits. this synchronous device achieves high speed double-data-rate transfer rates of up to 1066 mb/sec/pin (ddr2-1066) for general applications. the chip is designed to comply with the following key ddr2 sdram features: (1) posted cas with additive latency, (2) write latency = read latency -1, (3) off-chip driver (ocd) impedance adjustment and on die termination (4) normal and weak strength data output driver. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and /ck falling). all i/os are synchronized with a pair of bidirectional strobes (dqs and /dqs) in a source synchronous fashion. the address bus is used to convey row, column and bank address information in a /ras and /cas multiplexing style. the 2gb ddr2 device operates with a single power supply: 1.8v 0.1v vdd and vddq. available package: fbga-84ball (with 0.8mm x 0.8mm ball pitch)
em44dm1688lbb nov. 2011 3/29 www.eorex.com ordering information part no organization max. freq package grade pb em44dm1688lbb-25f 128m x 16 ddr2-8 00-cl5 fbga-84b commercial free EM44DM1688LBB-187F 128m x 16 ddr2-1 066-cl7 fbga-84b commercial free parts naming rule
em44dm1688lbb nov. 2011 4/29 www.eorex.com pin assignment: top view 1 2 3 7 8 9 vdd nc vss a vssq /udqs vddq dq14 vssq udm b udqs vssq dq15 vddq dq9 vddq c vddq dq8 vddq dq12 vssq dq11 d dq10 vssq dq13 vdd nc vss e vssq /ldqs vddq dq6 vssq ldm f ldqs vssq dq7 vddq dq1 vddq g vddq dq0 vddq dq4 vssq dq3 h dq2 vssq dq5 vddl vref vss j vssdl ck vdd cke /we k /ras /ck odt ba2 ba0 ba1 l /cas /cs a10/ap a1 m a2 a0 vdd vss a3 a5 n a6 a4 a7 a9 p a11 a8 vss vdd a12 nc r nc a13 84ball fbga note: vddl and vssdl are power and ground for the dll.
em44dm1688lbb nov. 2011 5/29 www.eorex.com pin description (simplified) pin name function j8,k8 ck,/ck (system clock) ck and ck are differential clock i nputs. all address and control input signals are sampled on the crossi ng of the positive edge of ck and negative edge of ck. output (read) data is referenced to the crossings of ck and ck (both directions of crossing). l8 /cs (chip select) all commands are masked when cs is registered high. cs provides for external rank selection on syst ems with multiple ranks. cs is considered part of the command code. k2 cke (clock enable) cke high activates and cke low deactivates internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self- refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit and fo r self-refresh entry. cke is asynchronous for self-refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck, odt and cke are disabled during power down. input buffers, excluding cke are disabled during self-refresh. m8,m3,m7,n2, n8,n3,n7,p2, p8,p3,m2,p7, r2,r8 a0~a13 (address) provided the row address (ra0 ? ra 13) for active commands and the column address (ca0-ca9) and auto precharge bit for read/write commands to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1 & ba2. the address inputs also provide the op-code during mode register set commands. l2,l3,l1 ba0, ba1,ba2 (bank address) ba0 ? ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. k9 odt (on die termination) odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is applied to each dq, udqs/udqs, ldqs/ldqs, udm, and ldm signal. the odt pin will be ignored if the extended mode register emrs(1) is programmed to disable odt. k7, l7, k3 /ras,/cas,/we (command inputs) /ras, /cas and /we (along with /cs) define the command being entered.
em44dm1688lbb nov. 2011 6/29 www.eorex.com pin description (continued) (data strobe) output with read data, input with write data. edge-aligned with read data, centered in write data. ldqs corresponds to the data on dq0-dq7; udqs corresponds to the data on dq8-dq15. the data strobes ldqs and udqs may be used in single ended mode or paired with optional complementary signals /ldqs and /udqs to provide differential pair signaling to the system during both reads and writes. an emrs(1) control bit enables or disables all complementary data strobe signals. in this data sheet, "differential dqs signals" refers to a10 = 0 of emrs(1) using ldqs/ldqs and udqs/udqs. "single-ended dqs signals" refers to a10 = 1 of emrs(1) using ldqs and udqs. udqs,/udqs , ldqs,/ldqs b7,a8,f7,e8 (input data mask) b3,f3 udm,ldm dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. g8,g2,h7,h3, h1,h9,f1,f9, c8,c2,d7,d3, d1, d9,b1,b9 (data input/output) data inputs and outputs are on the same pin. dq0~15 a1,e1,j9,m9, r1/ a3,e3,j3, n1,p9 (power supply/ground) vdd/vss vdd and vss are power supply for internal circuits. a9,c1,c3,c7, c9,e9,g1,g3, g7,g9/a7,b2, (dq power supply/dq ground) vddq and vssq are power supply for the output buffers. vddq/vssq b8,d2,d8,e7, f2,f8,h2,h8 j1/j7 vddl/vssdl (dll power supply/dll ground) vddl and vssdl are power supply for dll circuits j2 vref (reference voltage) sstl_1.8 reference voltage (no connection) a2,e2,r3,r7 nc no internal electrical connection is present.
em44dm1688lbb nov. 2011 7/29 www.eorex.com absolute maximum rating symbol item rating units v in , v out input, output voltage -0.5 ~ +2.3 v v dd power supply voltage -1.0 ~ +2.3 v v ddq power supply voltage -0.5 ~ +2.3 v v ddl dll power supply voltage -0.5 ~ +2.3 v t op operating temperature range commercial 0 ~ +70 c t stg storage temperature range -55 ~ +100 c p d power dissipation 1 w note: caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this spec ification. exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. recommended dc operating conditions (t a =-0c ~+70c) symbol parameter min. typ. max. units v dd power supply voltage 1.7 1.8 1.9 v v ddl power supply for dll voltage 1.7 1.8 1.9 v v ddq power supply for i/o voltage 1.7 1.8 1.9 v v ref i/o reference voltage 0.49 v ddq 0.50v ddq 0.51 v ddq v v tt i/o termination voltage v ref -0.04 v ref v ref +0.04 v v id dc differential input voltage -0.3 - v ref -0.15 v v ih input logic high voltage v ref +0.125 - v ddq +0.3 v v il input logic low voltage -0.3 - v ref -0.125 v
em44dm1688lbb nov. 2011 8/29 www.eorex.com recommended dc operating conditions (v dd =1.8v0.1v) -187(1066) -25(800) symbol parameter test conditions max units i dd1 operating current (note 1) iout = 0ma bl = 4, cl = cl(idd), al = 0 tck = tck(idd), trc = trc (idd) tras = trasmin(idd), trcd = trcd(idd) cke=high cs=high between valid commands address bus inputs are switching data pattern is same as idd4w 140 120 ma i dd2p precharge standby current in power down mode all banks idle tck = tck(idd), cke is low other control and address bus inputs are stable data bus inputs are floating 12 12 ma i dd2n precharge standby current in non-power down mode all banks idle all banks idle tck = tck(idd), cke is high, cs is high other control and address bus inputs are switching data bus inputs are switching 70 60 ma i dd3p active standby current in power down mode (a12=0) 35 30 ma i dd3p active standby current in power down mode (a12=1) all banks open tck = tck(idd), cke is low other control and address bus inputs are stable data bus inputs are floating 25 25 ma i dd3n active standby current in non-power down mode all banks open tck = tck(idd), tras = trasmax(idd) trp = trp(idd), cke is high cs is high between valid commands other control and address bus inputs are switching data bus inputs are switching 80 70 ma i dd4w 230 200 i dd4r operating current (burst mode) (note 2) all banks open, continuous burst writes bl = 4, cl = cl(idd), al = 0 tck = tck(idd), tras = trasmax(idd) trp = trp(idd), cke is high cs is high between valid commands address bus inputs are switching data bus inputs are switching 230 200 ma i dd5 refresh current (note 3) tck = tck(idd) refresh command at every trfc(idd) interval cke is high, cs is high between valid commands other control and address bus inputs are switching data bus inputs are switching 140 130 ma i dd6 self refresh current ck and ck at 0 v, cke 0.2 v other control and address bus inputs are floating, data bus inputs are floating 10 10 ma i dd7 operating current all bank interleaving reads iout = 0ma, bl = 4, cl = cl(idd) al = trcd(idd) - 1 x tck(idd) tck = tck(idd), trc = trc(idd) trrd = trrd(idd), tfaw = tfaw(idd) trcd = 1 x tck(idd), cke is high cs is high between valid commands address bus inputs are stable during deselects data pattern is same as idd4r 190 170 ma *all voltages referenced to vss. note 1: i dd1 depends on output loading and cycle rates . (cl=clmin, al=0) note 2: i dd4 depends on output loading and cycle rates . input signals switching note 3: min. of t rfc (auto refresh row cycle times) is shown at ac characteristics.
em44dm1688lbb nov. 2011 9/29 www.eorex.com recommended dc operating conditions (continued) symbol parameter test conditions min. max. units ioh output minimum source current *note1, 3, 4 -13.4 ma iol output minimum sink current *note2, 3, 4 +13.4 ma note1: vddq = 1.7 v; vout = 1.42 v. (vout-vddq) / io h must be less than 21 ohm for values of vout between vddq and vddq - 280 mv. note2: vddq = 1.7 v; vout = 280 mv. vout / iol must be less than 21 ohm for values of vout between 0v and 280 mv. note3: the dc value of vref applied to the receiving device is set to vtt. note4: the values of ioh(dc) and iol(dc) are based on the conditions given in note 1 and 2. they are used to test drive current capability to ensure vihmin plus a noise margin and vilmax minus a noise margin are delivered to an sstl_18 receiver. the act ual current values are derived by shifting the desired driver operating points along 21ohm load line to define a convenient current for measurement. note5: the vddq of the device under test is referenced.
em44dm1688lbb nov. 2011 10/29 www.eorex.com block diagram row add. buffer row decoder address register auto/ self refresh counter memory array s/ a & i/ o gating col. decoder col. add. buffer mode register set col add. counter burst counter dqm control data in data out dio a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a 10 a1 1 a1 2 ba0 ba1 timing register clk cke /cs / ras / cas /we dm udm,ldm /clk odt udqs, ldqs receiver write fifo driver dqs generator dll clk, /clk clk, /clk ba2 a1 3
em44dm1688lbb nov. 2011 11/29 www.eorex.com ocd default setting table parameter min. typ. max. units output impedance step size fo r ocd calibration 0 - 1.5 ? pull-up / pull-down mismatch 0 - 4 ? output slew rate 1.5 - 5.0 v/ns ac operating test conditions (v dd =1.8v0.1v) symbol parameter value units v swing (max.) input signal maximum peak to peak swing 1.0 v slew input signal minimum slew rate 1.0 v/ns v ref input reference level 0.5*v ddq v ac operating test conditions symbol parameter min. max. units v id ac differential input voltage 0.5 v ddq v v ix ac differential cross point input voltage 0.5*v ddq -0.175 0.5*v ddq +0.175 v v ox ac differential cross point output voltage 0.5*v ddq -0.125 0.5*v ddq +0.125 v v ih input logic high voltage v ref +0.2 v ddq +v peak v v il input logic high voltage v ssq -v peak v ref -0.2 v
em44dm1688lbb nov. 2011 12/29 www.eorex.com ac operating test characteristics (v dd =1.8v0.1v) -187 (ddr2-1066) -25 (ddr2-800) units symbol parameter min. max. min. max. t ac dq output access from clk,/clk -350 350 -400 400 ps t dqsck dqs output access from clk,/clk -350 350 -350 350 ps t cl ,t ch cl low/high level width 0.48 0.52 0.48 0.52 t ck t ck clock cycle time 1.875 8 2.5 8 ns t ds dq and dm setup time 50 - 50 - ps t dh dq and dm hold time 75 - 125 - ps t dipw dq and dm input pulse width for each input 0.35 - 0.35 - t ck t hz data out high impedance time from clk,/clk - t ac (max) - t ac (max) ns t lz (dq) dq low impedance time from clk,/clk 2*t ac (min) t ac (max) 2*t ac (min) t ac (max) ns t lz (dqs) dqs,/dqs low impedance time from clk,/clk t ac (min) t ac (max) t ac (min) t ac (max) ns t dqsq dqs-dq skew for associated dq signal - 175 - 200 ps t qhs data hold skew factor - 250 - 300 ps t dqss write command to first latching dqs transition -0.25 0.25 -0.25 0.25 t ck t dqsl ,t dqsh dqs low/high input pulse width 0.35 - 0.35 - t ck t dsl ,t dsh dqs input valid window 0.20 - 0.20 - t ck t mrd mode register set command cycle time 2 - 2 - t ck t wpres write preamble setup time 0 - 0 - ns t wpre write preamble 0.35 - 0.35 - t ck t wpst write postamble 0.4 0.6 0.4 0.6 t ck t is address/control input setup time (fast slew rate) 0.175 - 0.20 - ns t ih address/control input hold time (fast slew rate) 0.25 - 0.275 - ns t rpre read preamble 0.9 1.1 0.9 1.1 t ck
em44dm1688lbb nov. 2011 13/29 www.eorex.com ac operating test characteristics (continued) (vdd=1.8v0.1v) -187 (ddr2-1066) -25 (ddr2-800) symbol parameter min. max. min. max. units t rpst read postamble 0.4 0.6 0.4 0.6 t ck t ras active to precharge command period 40 70k 40 70k ns t rc active to active command period 56.25 - 57.5 - ns t rfc auto refresh row cycle time 127.5 - 127.5 - ns t rcd active to read or write delay 12.5 - 15 - ns t rp precharge command period 12.5 - 15 - ns t rrd active bank a to b command period 7.5 - 7.5 - ns t ccd column address to column address delay 2 - 2 - t ck t wr write recover time 15 - 15 - ns t dal auto precharge write recovery + precharge time t rp + t wr - t rp + t wr - ns t xard exit active power-down mode to read command (fast exit) 3 - 2 - t ck t xards exit active power-down mode to read command (slow exit) 10-al - 8-al - t ck t xp exit precharge power-down to any non-read command 3 - 2 - t ck t wtr internal write to read command delay 7.5 - 7.5 - ns t rtp internal read to precharge delay 7.5 - 7.5 - ns t xsnr exit self refresh to non-read command t rfc +10 - t rfc +10 - ns t xsrd exit self refresh to read command 200 - 200 - t ck t refi average periodic refresh interval - 7.8 - 7.8 us t cke cke minimum pulse width 3 - 3 - t ck t faw four active to row active delay (same bank) 35 35 ns t oit ocd drive mode output delay 0 12 0 12 ns
em44dm1688lbb nov. 2011 14/29 www.eorex.com ac operating test characteristics (continued) (vdd=1.8v0.1v) ddr2-800 ddr2-1066 symbol parameter min. max. min. max. units taond odt turn-on delay 2 - 2 - tck taofd odt turn-off delay 2.5 - 2.5 - tck taon odt turn-on (note1) t ac(min.) t ac(max) +0.7 t ac(min.) t ac(max) +2.575 ns taof odt turn-off (note2) t ac(min.) t ac(max) +0.6 t ac(min.) t ac(max) +0.6 ns taonpd odt turn-on in power-down mode t ac(min.) +2 2*tck + t ac(max) +1 t ac(min.) +2 2*tck + t ac(max) +1 ns taofpd odt turn-off in power-down mode t ac(min.) +2 2.5*tck + t ac(max) +1 t ac(min.) +2 2.5*tck + t ac(max) +1 ns tanpd odt to power-down mode entry latency 3 - 2.5 - tck taxpd odt power-down exit latency 8 - 11 - tck note 1: odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . note 2: odt turn off time min is when the device starts to turn off odt resistance odt turn off time max is when the bus is in high impedance. both are measured from t aofd .
em44dm1688lbb nov. 2011 15/29 www.eorex.com simplified state diagram
em44dm1688lbb nov. 2011 16/29 www.eorex.com 1. command truth table cke command symbol n-1 n /cs /ras /cas /we ba0 ~ ba2 a10 a12~a0 device deselect desl h x h x x x x x x no operation nop h x l h h h x x x read read h h l h l h v l v read with auto pre-charge reada h h l h l h v h v write writ h h l h l l v l v write with auto pre-charge writa h h l h l l v h v bank activate act h h l l h h v v v pre-charge select bank pre h h l l h l v l x pre-charge all banks pall h h l l h l x h x (ext.) mode register set emrs h h l l l l v* v v auto refresh ref h h l l l h x x x self refresh entry self h l l l l h x x x h l h x x x x x x power down entry pden h l l h h h x x x l h h x x x x x x power down exit pdex l h l h h h x x x h = high level, l = low level, x = high or low level (don't care), v = valid data input * please refers to the mrs, emrs(1) & emrs(2) setting 2. cke truth table cke item command symbol n-1 n /cs /ras /cas /we addr. any state *note1 - h h v v v v v all bank idle self refresh entry self h l l l l h x nop l h l h h h x self refresh self refresh exit desl l h h x x x x desl h l h x x x x all bank idle active or precharge power down entry nop h l l h h h x desl l h h x x x x power down power down exit nop l h l h h h x power down maintain power down - l l x x x x x self refresh maintain self refresh - l l x x x x x h = high level, l = low level, x = high or low level (don't care) note1: must be legal commands as defined in the comma nd truth table. and any state other than list above.
em44dm1688lbb nov. 2011 17/29 www.eorex.com 3. operative command table current state /cs /r /c /w addr. command action h x x x x desl nop l h h h x nop nop l h l h ba/ca/a10 read/reada illegal (note 1) l h l l ba/ca/a10 writ/writa illegal (note 1) idle l l h h ba/ra act bank active,latch ra nop (note 3) l l h l ba, a10 pre/prea auto/self refresh (note 4) l l l h x ref/self l l l l op-code, mode-add mrs/emrs(1)(2) mode register h x x x x desl nop l h h h x nop nop begin read,latch ca, determine auto-precharge l h l h ba/ca/a10 read/reada begin write,latch ca, determine auto-precharge l h l l ba/ca/a10 writ/writa bank active l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea precharge/precharge all l l l h x ref/self illegal (note 1) l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) h x x x x desl row active(continue burst to end) l h h h x nop row active(continue burst to end) l h l h ba/ca/a10 read/reada burst interrupt read l h l l ba/ca/a10 writ/writa illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba, a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) h x x x x desl write recovering (continue burst to end) l h h h x nop write recovering (continue burst to end) l h l h ba/ca/a10 read/reada illegal (note 1) l h l l ba/ca/a10 writ/writa burst interrupt l l h h ba/ra act illegal (note 1) l l h l ba, a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) write l l l l op-code, mrs/emrs(1)(2) illegal (note 1)
em44dm1688lbb nov. 2011 18/29 www.eorex.com 3. operative command table (continued) current state /cs /r /c /w addr. command action precharging (continue burst to end) h x x x x desl precharging (continue burst to end) l h h h x nop l h l h ba/ca/a10 read/reada illegal (note 1) illegal (note 1) l h l l ba/ca/a10 writ/writa l l h h ba/a10 act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) read with ap l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) write recover with auto precharge (continue burst to end) h x x x x desl write recover with auto precharge (continue burst to end) l h h h x nop l h l h ba/ca/a10 read/reada illegal (note 1) l h l l ba/ca/a10 writ/writa illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) write with ap l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) h x x x x desl nop(idle after trp) l h h h x nop nop(idle after trp) l h l h ba/ca/a10 read/reada illegal (note 1) l h l l ba/ca/a10 writ/writa illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea nop(idle after trp) (note 3) l l l h x ref/self illegal (note 1) pre-charging l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) h x x x x desl nop(row active after trcd) l h h h x nop nop(row active after trcd) illegal (note 1) l h l h ba/ca/a10 read/reada illegal (note 1) l h l l ba/ca/a10 writ/writa l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) row activating l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) h = high level, l = low level, x = high or low level (don't care), ap = auto pre-charge
em44dm1688lbb nov. 2011 19/29 www.eorex.com 3. operative command table (continued) current state /cs /r /c /w addr. command action nop (enter bank active after twr) h x x x x desl nop (enter bank active after twr) l h h h x nop illegal (note 1) l h l h ba/ca/a10 read new write, determine ap write l h l l ba/ca/a10 writ/writa illegal (note 1) l l h h ba/ra act l l h l ba/a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) recovering l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) nop(idle after t rfc ) h x x x x desl nop(idle after t rfc ) l h h h x nop illegal (note 1) l h l h ba/ca/a10 read/reada illegal (note 1) l h l l ba/ca/a10 writ/writa l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x ref/self illegal (note 1) refreshing l l l l op-code, mode-add mrs/emrs(1)(2) illegal (note 1) h = high level, l = low level, x = high or low level (don't care), ap = auto pre-charge note 1: illegal to bank in specified states; function may be legal in the bank indica ted by bank address (ba), dependi ng on the state of that bank. note 2: must satisfy bus contention, bus turn ar ound, and/or write recovery requirements. note 3: nop to bank precharging or in idle stat e.may precharge bank indicated by ba. note 4: illegal of any bank is not idle.
em44dm1688lbb nov. 2011 20/29 www.eorex.com 4. command truth table for cke current state c ke /cs /r /c /w addr. action invalid h x x x x x x exist self-refresh l h h x x x x exist self-refresh l h l h h h x illegal self refresh l h l h h l x illegal l h l h l x x illegal l h l l x x x nop(maintain self refresh) l l x x x x x invalid h x x x x x x exist power down l h h x x x x exist power down both bank l h l h h h x illegal precharge l h l h h l x illegal power down l h l h l x x illegal l h l l x x x nop(maintain power down) l l x x x x x refer to function true table h h x x x x x enter power down mode (note 3) h l h x x x x enter power down mode (note 3) h l l h h h x illegal h l l h h l x illegal all banks idle h l l h l x x row active/bank active h l l l h h ra enter self-refresh (note 3) h l l l l h x mode register access h l l l l l op-code special mode register access h l l l l l op-code refer to current state l x x x x x x any state other than listed above h h x x x x x refer to command truth table h = high level, l = low level, x = high or low level (don't care) notes 1: after cke?s low to high transition to exist self refresh mode.and a time of t rc (min) has to be elapse after cke?s low to high transition to issue a new command. notes 2: cke low to high transition is asynchronous as if restarts internal clock. notes 3: power down and self refresh can be entered only from the idle state of all banks. 5. bank selection signal table bank\signal ba0 ba1 ba2 bank0 l l l bank1 h l l bank2 l h l bank3 h h l bank4 l l h bank5 h l h bank6 l h h bank7 h h h note: h:vih, l:vil
em44dm1688lbb nov. 2011 21/29 www.eorex.com initialization the following sequence is required for power-up and initialization and is shown in below figure: 1. apply power and attempt to maintain cke below 0.2 * vddq and odt at a low state (all other inputs may be undefined). to guarantee odt off, vref must be valid and a low level must be applied to the odt pin. - vdd, vddl and vddq are driven from a single powe r converter output, and vtt is limited to 0.95 v max, and vref tracks vddq/2 or - apply vdd before or at the same time as vddl; ap ply vddl before or at the same time as vddq; - apply vddq before or at the same time as vtt & vref . at least one of these two sets of conditions must be met. 2. start clock (ck, /ck) and maintain stable power and clock condition for a minimum of 200 s. 3. apply nop or deselect commands & take cke high. 4. wait minimum of 400ns, then issue a precharge-all command. 5. issue reserved command emrs(2) or emrs(3). 6. issue emrs(1) command to enable dll. (a0=0 and ba0=1 and ba1=0) 7. issue mrs command (mode register set) for "dll reset". (a8=1 and ba0=ba1=0) 8. issue precharge-all command. 9. issue 2 or more auto-refresh commands. 10. issue a mrs command with low on a8 to initia lize device operation. (without resetting the dll) 11. at least 200 clocks after step 8, execute ocd cali bration (off chip driver impedance adjustment). if ocd calibration is not used, emrs ocd default command (a9=a8=a7=1) followed by emrs(1) ocd calibration mode exit command (a9=a8=a7=0) must be issued with other parameters of emrs(1). 12. the ddr2 sdram is now initialize d and ready for norm al operation.
em44dm1688lbb nov. 2011 22/29 www.eorex.com mode register definition mode register set the mode register stores the data fo r controlling the various operating modes of ddr2 sdram which contains addressing mode, burst length, /cas latenc y, wr (write recovery), test mode, dll reset and various vendor?s specific opinions. the defaults value of the register is not defined, so t he mode register must be written after power up for proper ddr2 sdram operation. the mode register is writt en by asserting low on /cs, /ras, /cas, /we and ba0/1. the state of the address pins a0-a12 in the same cycle as /cs, /ras, /cas, /we and ba0/1 going low is written in the mode register. two clock cycles are requested to complete the writ e operation in the mode register. the mode register contents can be changed using the same command and cloc k cycle requirements during operating as long as all banks are in the idle state. the mode register is divided into various fields d epending on functionality. the burst length uses a0-a2, addressing mode uses a3, /cas latency (read latency from column address) uses a4-a6. a7 is used for test mode. a8 is used for ddr reset. a9 ~ a11 are used for write recovery time (wr), a7 must be set to low for normal mrs operation. with address bit a12 two power- down modes can be selected, a ?standard mode? and a ?low-power? power-down mode.
em44dm1688lbb nov. 2011 23/29 www.eorex.com address input for mode register set
em44dm1688lbb nov. 2011 24/29 www.eorex.com burst type (a3) burst length a2 a1 a0 sequential addressing interleave addressing x 0 0 0 1 2 3 0 1 2 3 x 0 1 1 2 3 0 1 0 3 2 x 1 0 2 3 0 1 2 3 0 1 4 x 1 1 3 0 1 2 3 2 1 0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 8 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 *page length is a function of i/o organization and column addressing write recovery wr (write recovery) is for writes with auto-prechar ge only and defines the time when the device starts pre-charge internally. wr must be programmed to match the minimum requirement for the analogue t wr timing. power-down mode active power-down (pd) mode is defined by bit a12. pd mode allows the user to determine the active power-down mode, which determines performance vs. power savings. pd mode bit a12 does not apply to precharge power-down mode. when bit a12 = 0, standar d active power-down mode or ?fast-exit? active power-down mode is enabled. the t xard parameter is used for ?fast-exit? active power-down exit timing. the dll is expected to be enabled and running during this mode. when bit m12 = 1, a lower power active power-down mode or ?slow-exit? active power-down mode is enabled. the t xards parameter is used for ?slow-exit? active power-down exit timing. the dll ca n be enabled, but ?frozen? during active power-down mode since the exit-to-read command timing is re laxed. the power difference expected between pd ?normal? and pd ?low-power? mode is defined in the idd table.
em44dm1688lbb nov. 2011 25/29 www.eorex.com extended mode register set emrs(1 ) the emrs (1) is written by asserting low on /cs, /r as, /cas, /we,ba1 and high on ba0 ( the ddr2 should be in all bank pre-charge with cke already prior to wr iting into the extended mode register. ) the extended mode register emrs(1) stores the dat a for enabling or disabling the dll, output driver strength, additive latency, ocd program, odt, dqs and output buffers disable, rqds and rdqs enable. the default value of the extended mode register em rs(1) is not defined, therefore the extended mode register must be written after power-up for proper operation. the mode register set command cycle time (t mrd ) must be satisfied to complete the write operation to the emrs(1). mode register contents can be changed using the same command and clock cycle requirements during normal operati on when all banks are in pre-charge state. 0 a13 dll dic rtt additive latency rtt ocd program /dqs rdqs qoff a0 a1a2 a3a4a5a6a7a8a9 a10 a11 a12 1 1 50 ohm 0 1 150 ohm 1 0 75 ohm 0 0 odt disable a2 a6 rtt weak (60%) normal (100%) output driver impedance control 1 1 1 reserved 0 1 1 6 1 0 1 5 0 0 1 4 1 1 0 3 0 1 0 2 1 0 0 1 0 0 0 0 a3 a4 a5 additive latency 1 disable 0 enable a10 /dqs 1 0 a11 1 1 1 (*2) 0 0 1 (*1) 0 0 1 0 0 0 0 0 a7 a8 1 1 0 1 1 0 0 0 ba0 ba1 1 0 a0 *1: when adjust mode is issued, al from previously set value must b e applied. *2: after setting to default, ocd mode needs to be exited by settin g a9 a7 to 000. refer to the section off - chip driver (ocd) impedance adjustment for detail information 10 ba0 ba1 1 1 50 ohm * 0 1 150 ohm 1 0 75 ohm 0 0 odt disable a2 a6 rtt 1 0 a1 1 1 1 reserved 0 1 1 reserved 1 0 1 5 0 0 1 4 1 1 0 3 0 1 0 2 1 0 0 1 0 0 0 0 a3 a4 a5 additive latency 1 disable 0 enable a10 /dqs 1 enable 0 disable a11 rdqs enable 1 disabled 0 enabled a12 qoff (output buffer) 1 1 1 ocd calibration default (*2) 0 0 1 adjust mode (*1) 0 1 0 drive (0) 1 0 0 drive (1) 0 0 0 ocd calibration mode exit a7 a8 a9 ocd calibration program 1 1 emrs(3) reserved 0 1 emrs(2) 1 0 emrs(1) 0 0 mrs ba0 ba1 mrs mode 1 disable 0 enable a0 dll * - - ba2 0
em44dm1688lbb nov. 2011 26/29 www.eorex.com output drive strength the output drive strength is defined by bit a1. norm al drive strength outputs are specified to be sstl_18. programming bit a1 = 0 selects normal ( 100 %) drive strength for all outputs. programming bit a1 = 1 will reduce all outputs to approximately 60 % of the sstl_18 drive strength. this option is intended for the support of the lighter load and/or point-to-point environments. single-ended and differential data strobe signals emrs strobe function matrix signals a11 (/rdqs enable) a10 (/dqs enable) rdqs dm /rdqs dqs /dqs 0 (disable) 0 (enable) dm hi-z dqs /dqs differential dqs signal 0 (disable) 1 (disable) dm hi-z dqs hi-z single-ended dqs signal 1 (enable) 0 (enable) rdqs /rdqs dqs /dqs differential dqs signal 1 (enable) 1 (disable) rdqs hi-z dqs hi-z single-ended dqs signal output disable (qoff) under normal operation, the dram outputs are enabled during read operation for driving data qoff bit in the emrs(1) is set to (0). when the qoff bit is set to 1, the dram outputs will be disabled. disabling the dram outputs allows users to measure idd currents during read operations, without including the output buffer current.
em44dm1688lbb nov. 2011 27/29 www.eorex.com address input for extended mode register set emrs(2) & emrs(3)
em44dm1688lbb nov. 2011 28/29 www.eorex.com on-die termination (odt) odt (on-die termination) is a new feature on dd r2 components that allows a dram to turn on/off termination resistance for each udq, ldq, udqs, udqs, ldqs, ldqs, udm and ldm signal via the odt control pin for x16 configuration, where udqs and ldqs are terminated only when enabled in the emrs(1) by address bit a10 = 0. the odt feature is designed to improve signal inte grity of the memory channel by allowing the dram controller to independently turn on/off termination resistance for any or all dram devices. the odt function can be used for all active and standby modes. odt is turned off and not supported in self- refresh mode. odt function switch sw1 or sw2 is enabled by the odt pin. selection between sw1 or sw2 is determined by ?rtt (nominal)? in emrs(1) address bits a6 & a2. target rtt = 0.5 * rval1 or 0.5 * rval2. the odt pin will be ignored if the emrs (1) is programmed to disable odt.
em44dm1688lbb nov. 2011 29/29 www.eorex.com package description: 84ball-fbga solder ball: lead free (sn-ag-cu) a b c d e f g h j k l m n p r 9 8 7 6 5 4 3 2 1 6.40 unit: mm 0.80 12.50 0.10 a1 8.000.10 11.20 5.60 0.05 1.6 1.2 max 0.45 0.05 0.10 max 0.25 ~ 0.40 0.80

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